Meet Averlogic´s Panel Display Test Solution
Averlogic Panel Display Test Solution
Averlogic´s FIFO will prevent Screen Defective Pixels on LCD Displays during manufacture process

Every smartphone or LCD display manufacturer is susceptible to defects, but the consumers have little tolerance for such issues.

Averlogic’ Panel Display Test Solution will improve the efficiency of the inspections and lead to further improvements in quality of in-house engineering assuring the client´s satisfaction.

Averlogic´s FIFOs, AL462, can prevent screen defective pixels during manufacture process through a video pattern generator.

Averlogic´s Panel Display Test Solution block diagram:

Averlogic Panel Display Test Solution Block Diagram

Averlogic´s Panel Display Test Solution potential scenarios:

Panel Display Test Solution Scenarios
Main Features
  • 32-bit data input and output bus
  • Write one frame pattern into FIFO memory by CPLD
  • Use Video V-SYNC signal to lock one frame pattern in FIFO memory
  • Use pixel clock to synchronize/write frame data/pattern to FIFO memory
  • Put video pattern on panel by CPLD
  • Use CPLD to generate display timing and move pattern from FIFO memory to screen defective pixel
Do you want to design a Panel Display Test Solution?
View this email in your browser
You are receiving this email because of your relationship with AverLogic Technologies, Corp.. Please reconfirm your interest in receiving emails from us. If you do not wish to receive any more emails, you can unsubscribe here.
This message was sent from to
4F., No.43, Lane 188, Rui Guang Rd., Nei-Hu Dist.,, Taipei, Taipei 114, Taiwan

Update Profile/Email Address | Forward Email | Report Abuse